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? 1990 burr-brown corporation pds-1075a printed in u.s.a. march, 1992 cmp100 high-speed window comparator ate pin receiver features l propagation delay: 5ns max, 100mv overdrive l common mode input range: 12v l input impedance: 120k w || 2pf l outputs: latchable, 10k ecl compatible l complete: no external parts required l temperature range: C25 c to +85 c l packages: 16-pin plastic dip, 16-lead plastic soic applications l ate pin receiver l window comparator l threshold detector description cmp100 is a high-speed dual comparator designed for use as an automatic test system pin receiver. it is also useful in a wide variety of analog threshold detector and window comparator applications. cmp100 has two reference inputs and one analog input which is common to both comparators. all in- puts are attenuated by a voltage divider to provide high common mode voltage operation. the analog input attenuator is r-c tuned to optimize operation with high-speed input waveforms. the reference input attenuators are not r-c tuned. each attenuator net- work is followed by a buffer amplifier ahead of the comparator circuits. complementary ecl output stages are capable of driving 50 w terminated transmission lines to a C2v pull-down voltage. in addition, latch-enable inputs are provided for each comparator, allowing operation as a sampling comparator. cmp100 is available as an industrial temperature range device, C25 c to +85 c, and is packaged in a 16-pin plastic dip and in a 16-lead plastic soic. q 1 acom 1 1 1 1 v ref 2 analog in v ref 1 le 1 le 1 q 1 dcom pwr com v q 2 q 2 le 2 le 2 2 3 v+ 11 12 14 13 4 5 16 9 7 10 8 15 1 6 international airport industrial park ? mailing address: po box 11400 ? tucson, az 85734 ? street address: 6730 s. tucson blvd. ? tucson, az 85706 tel: (602) 746-1111 ? twx: 910-952-1111 ? cable: bbrcorp ? telex: 066-6491 ? fax: (602) 889-1510 ? immediate product info: (800) 548-6132
2 cmp100 absolute maximum ratings v+ to digital common and power common ....................................... +6v vC to digital common and power common ....................................... C6v (v+) C (vC) ........................................................................................... 12v digital inputs to digital common differential ......................................................................................... 4v common mode ......................................................................... vC to v+ differential analog input voltage ....................................................... 25v package power dissipation ........................................................... 750mw storage temperature ...................................................... C60 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c stresses exceeding those listed above may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin definitions pin name description 1, 15 le2, le2 latch or unlatch comparator 1 outputs 2, 3 q2, q2 ecl outputs of comparator 2 4 dcom return for comparator circuits 5 pwrcom return for ecl output transistor currents 6, 7 q1, q1 ecl outputs of comparator 1 8, 10 le1, le1 latch or unlatch comparator 2 outputs 9 v+ positive supply voltage, +5v 11 v ref 1 reference voltage for comparator 1 12 analog in analog signal input 13 acom return for analog in, v ref 1 , v ref 2 14 v ref 2 reference voltage for comparator 2 16 vC negative supply voltage: (ecl supply, C5.2v) specifications electrical t a = 25 c and at rated supplies: v+ = +5v, vC = C5.2v unless otherwise noted. cmp100ap, au parameter min typ max units analog inputs differential input voltage range 24 v common mode voltage range 12 v resistance reference inputs: v ref 1 , v ref 2 45 60 75 k w analog input 90 120 150 k w capacitance, all inputs 2pf transfer characteristics accuracy input offset voltage, v os (1) 10 20 mv common mode error 10 mv/v voltage offset drift 100 250 m v/ c power supply sensitivity of offset: d v os / d v+ 10 m v/v d v os / d vC 10 m v/v response time propagation delay, t pd (2, 3) 100mv overdrive, latch disabled 3.6 5 ns digital signals (4) (over specification temperature range) inputs (latch controls) logic levels: v ih C1.1 v v il C1.5 v i ih (v i = C1.1v) 50 m a i il (v i = C1.5v) 5 m a outputs (balanced) logic levels: v ol (50 w load to C2v) C1.5 v v oh (50 w load to C2v) C1.1 v power supply requirements supply voltage v+ +4.75 +5 +5.25 vdc vC C5.45 C5.2 C4.95 vdc supply current (5) v+ +30 +40 ma vC C40 C50 ma power dissipation (6) 360 460 mw temperature range specification C25 +85 c storage C65 +150 c notes: (1) defined as half the magnitude between low-to-high and high-to-low transition input voltages. (2) see section on measuring cmp100 performance. (3) see discussion of specifications for exact conditions. (4) 10k ecl compatible. (5) maximum supply current is specified at typical supply voltages. (6) maximum power dissipation is calculated with typical supply voltages and maximum currents. note that dissipation in the output transistors from driving 50 w ecl loads will increase the total power dissipation by about 50mw.
3 cmp100 mechanical p package 16-pin plastic dip a a 1 b 1 b c k n d h g f l m j p pin 1 inches millimeters dim min max min max a .740 .800 18.80 20.32 a 1 .725 .785 18.42 19.94 b .230 .290 5.85 7.38 b 1 .200 .250 5.09 6.36 c .120 .200 3.05 5.09 d .015 .023 0.38 0.59 f .030 .070 0.76 1.78 g .100 basic 2.54 basic h 0.20 .050 0.51 1.27 j .008 .015 0.20 0.38 k .070 .150 1.78 3.82 l .300 basic 7.63 basic m0 15 0 15 n .010 .030 0.25 0.76 p .025 .050 0.64 1.27 note: leads in true position within 0.01" (0.25mm) r at mmc at seating plane. u package 16-pin soic a b n h d j g l 1 b a 1 m pin 1 identifier c inches millimeters dim min max min max a .400 .416 10.16 10.57 a 1 .388 .412 9.86 10.46 b .286 .302 7.26 7.67 b 1 .268 .286 6.81 7.26 c .093 .109 2.36 2.77 d .015 .020 0.38 0.51 g .050 basic 1.27 basic h .022 .038 0.56 0.97 j .008 .012 0.20 0.30 l .391 .421 9.93 10.69 m5 typ 5 typ n .000 .012 0.00 0.30 note: leads in true position within 0.01" (0.25mm) r at mmc at seating plane. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. ordering information model package cmp100ap 16-pin dip CMP100AU 16-lead soic
4 cmp100 typical performance curves t a = 25 c and at rated supplies: v+ = +5v, vC = C5.2v unless otherwise noted. note: propagation delay vs overdrive is shown for two amplitudes of input pulse: from C200mv ? +v od (0.2nv/ns slew rate) and C1v ? +v od (1v/ns slew rate). for an inverse input waveform: from +1v ? Cv od and from +200mv ? Cv od , propagation delays identical to those above are produced. 21 18 15 12 9 6 3 0 0 100 200 300 400 500 propagation delay (ns) overdrive (mv) 0v v od v 150ns 50ns propagation delay vs overdrive v ref 1 = v ref 2 = 0v ?v od ? +v ?00mv od ? +v response to a 3ns analog input pulse 2.76ns q q 400 200 0 ?00 ?00 analog input (mv) digital output (200mv/div) time (1ns/div) analog in 60 40 20 0 ?0 ?0 10 30 50 70 90 ambient temperature (?) power supply current (ma) ?.2v +5v power supply current vs ambient temperature 5 4 3 2 1 0 300 306090 ambient temperature (?) propagation delay (ns) 0v 100mv 200mv 150ns 50ns v ref 1 = v ref 2 = 0v propagation delay vs ambient temperature
5 cmp100 typical performance curves (cont) t a = 25 c and at rated supplies: v+ = +5v, vC = C5.2v unless otherwise noted. response to a 2ns latch enable pulse q q le t dlol 400 200 0 ?00 ?00 analog input (mv) digital output (200mv/div) time (5ns/div) analog in capturing a narrow analog pulse q q 3.5ns le 400 200 0 ?00 ?00 analog input (mv) digital output (200mv/div) time (2ns/div) analog in q q le setup time, t s t s 400 200 0 ?00 ?00 analog input (mv) digital output (200mv/div) time (2ns/div) analog in
6 cmp100 discussion of specifications analog input offset voltage, v os the value of the the comparison threshold for v ref 1 or v ref 2 = 0v. v os and maximum drift vs temperature of v os are guaranteed. common mode error as v ref varies over its range, there is a small gain error which manifests itself as a change in the comparison level. common mode error drifts typically C15 m v/ o c. dynamic performance figure 1 illustrates the following analog and logic perform- ance definitions. input to output high propagation delay, t pdh t pdh is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (q output) low-to-high transition. output logic is not latched for this definition. input to output low propagation delay, t pdl t pdl is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (q output) high-to-low transition. output logic is not latched for this definition. the propagation delay of the cmp100 is virtually identical for negative going and positive going analog input edges. differential propagation delay (skew), t diff t diff is the difference in propagation delay from one com- parator to another. the skew between each half of one cmp100 is no greater than 200ps. propagation delay dispersion propagation delay dispersion is the variation in propagation delay versus input overdrive. note that propagation delay may also be a function of input slew rate and of the previous level. the input waveform for the propagation delay specification is illustrated in the first typical performance curve, propa- gation delay vs overdrive. the propagation delay listed in the electrical specifications table is specified using an input waveform with 100mv overdrive, a previous level of C200mv and a slew rate of 200v/ m s. a typical propagation delay curve is also shown for a previous level of C1v. the outputs are not latched for this specification. overdrive overdrive is the voltage by which the input exceeds v ref v os . minimum set-up time, t s t s is the minimum time before the positive transition of the latch enable (le) that an analog input signal change must be present in order to be acquired and held at the outputs. t pdl v ref 2 q 2 q 2 analog in 0v le 2 le 2 t ldoh t h t s v ref 1 q 1 le 1 t pw t ldol t pdh le 1 q 1 figure 1. analog and logic timing definitions.
7 cmp100 the t s performance of cmp100 is illustrated in the typical performance curves. minimum hold time, t h t h is the minimum time after the positive transition of the latch enable (le) that an analog input signal must remain unchanged in order to be acquired and held at the outputs. t h = 0 for cmp100. logic performance definitions latch enable to output high delay, t dloh t dloh is the propagation delay of latch logic circuits measured from the 50% point of the latch enable signal (le) high- to-low transition to the 50% point of an output (q) low-to- high transition. latch enable to output low delay, t dlol t dlol is the propagation delay of latch logic circuits meas- ured from the 50% point of the latch enable signal high-to- low transition to the 50% point of an output (q) high-to- low transition. minimum latch enable pulse width, t pw t pw is the minimum time that the latch enable (le) must be high in order to acquire and hold an input signal change. the actual timing performance of cmp100 is illustrated in the typical performance curves. operating considerations input voltage input reference voltages v ref 1 and v ref 2 may vary from C12v to +12v. the frequency-compensated analog input network can also swing from C12v to +12v. care must be taken to be sure that the maximum differential input voltage is not exceeded. that is, the voltage between analog in and v ref 1 or between analog in and v ref 2 must not exceed 25v. if this voltage is exceeded by 1 or 2 volts, even momentarily, emitter-base voltage breakdown of the input transistors will occur and cause a permanent shift of the offset voltage, v os , to an out-of-spec value. however, the cmp100 will continue to function and will not be destroyed. input voltages to the cmp100 of uncontrolled magnitude may occur during system power-up. take care to assure that the absolute maximum differential input voltage is not exceeded during power-up. driving source impedance an apparent slow response of the cmp100 may be due a combination of high source impedance and stray capacitance to ground at the analog input. an r-c combination of 1k w source resistance and 10pf to ground results in a 10ns time constantmore than double the typical response time of the cmp100. the latch function the latch function is used for sampling the state of the outputs and holding them until the output can be processed. figure 1 shows a timing diagram for differential input latch enable controls, le and le. the latches of the cmp100 are transparent type latches. if le is low (le is high), the q outputs indicate the sign of the input difference voltage. when le goes high (le low), the comparator outputs are held at the current state. when the analog input signal passes through the reference level, the comparator output q changes, after a time of t pdh or t pdl . however, if the output is to be latched, the input signal must have crossed the threshold for a time t s (set-up time) before the rising edge of le occurs in order to capture the correct output state. on the other hand, in order to capture a correct output state just before it changes, it is necessary to maintain that output state for t h , (hold time) after the rising edge of le. t h = 0 for cmp100. a minimum latch pulse width of t pw is needed to capture the state of narrow pulses. see the typical performance curves for an example of sampling a narrow pulse. 10k ecl logic if the latching function is not used, the latch enable inputs (le 1 and le 2 ) should be returned to an ecl high voltage (C0.8v) or to digital common (0v). le 1 and le 2 should be returned to an ecl low level (C1.8v), to an ecl bias voltage (C1.3v) or to the C2v 50 w load pull-down power supply. connecting an ecl input to C5.2v may create a marginal transistor emitter-base breakdown situation over the ambient temperature range and is not recommended. if a single (non-differential) ecl logic input is used, connect the complementary input to an ecl bias voltage (C1.3v). 100k ecl logic the negative power supply, vC, of the cmp100 can be operated at C4.5v. the common mode input range of the analog and reference inputs will be reduced to +12v to C7.5v. output levels are not affected by changing the vC power supply voltage to C4.5v. ttl inputs the operating common mode range of a logic input is C2v to +2v. thus one can bias the logic inputs to use them with ttl inputs if the high input level is maintained below +2v. in this case, the complementary logic input should be biased at the ttl threshold of +1.4v. level shifting ecl to ttl the ecl outputs can be translated to ttl using a motorola mc10125 quad ecl-ttl translator. the logic delay t dloh and t dlol and the propagation delay t pdl and t pdh will be increased by the delay of the translator.
8 cmp100 solution for preserving dynamic performance and reducing noise coupling into sensitive circuits. when passing power through a connector, use every avail- able spare pin for making power supply return connections, and use some of the pins as a faraday shield to separate the analog and digital common lines. power supply returns (acom, dcom and pwrcom) for best performance, connect acom (pin 13) and dcom (pin 4) to the ground plane under the comparator. pwrcom (pin 5), which is connected to the collectors of the ecl outputs, can be returned by separate printed circuit trace but its inductance should be kept low to avoid ringing. do not connect acom and dcom together at the end of a long printed circuit trace and then run a single wire to the power supply. to use separate acom and dcom return printed circuit traces, connect a 1 m f to 47 m f tantalum capacitor between dcom and acom pins as close to the package as possible. power supply bypassing every power supply line leading into the comparator must be bypassed to the common pins. the bypass capacitor should be located as close to the comparator package as possible and tied to a solid return, preferably to the ground plane under the device. if the capacitors are not close enough to the package, dc resistance and inductance may be above acceptable levels. use tantalum capacitors with values of from 1 m f to 10 m f. parallel them with smaller ceramic installation terminating ecl outputs the best performance will be achieved with the use of proper ecl terminations. such a configuration is illustrated in figure 3. the open-emitter outputs of the cmp100 are designed to be terminated through 50 w resistors to C2v or any other equivalent termination. if high-speed ecl signals must be routed more than a few centimeters, microstrip or stripline techniques may be required to insure proper tran- sition times and prevent output ringing. power supply selection linear power supplies are preferred. although switching power supply rms specifications may appear to indicate low noise output, voltage spikes generated by switchers may be hard to filter. their high-frequency components may be extremely difficult to keep out of the power supply return system. if switchers must be used, their outputs must be carefully filtered and the power supply itself should be shielded and located as far away as possible from precision analog circuits. printed circuit layout considerations power supply wiring use heavy power supply and power supply common (ground) wiring. a ground plane under the part is usually the best figure 2. circuit for evaluating analog propagation delay, t pdh , t pdl . q 1 acom v ref 2 analog in v ref 1 le 1 le 1 q 1 dcom pwr com v q 2 q 2 le 2 le 2 2 3 v+ 11 12 14 13 4 5 16 16.6 w 16.6 w 16.6 w scope to 50 w generator +5v 1? 0.1? 16.6 w 16.6 w 16.6 w 16.6 w to 50 scope w 1 15 9 7 6 ?.2v 00 w 1 0.1? 1? 1? 0.1? 66.5 w 66.5 w ?v cmp100 00 w 1 from 50 w 49.9 w 10 8
9 cmp100 capacitors for high frequency filtering if necessary. electro- lytic capacitors are not recommended because their high frequency response is poor. separate the analog and digital signals digital signal paths entering or leaving the layout should have minimum length to minimize crosstalk to analog wir- ing. stray capacitive feedback from digital outputs to the analog input may cause the outputs to appear fuzzy well after the outputs have changed. keep analog signals as far away as possible from digital signals. if they must cross, cross them at right angles. coaxial cable may be necessary for analog inputs in some situations. measuring cmp100 performance using an oscilloscope oscilloscope probes should be matched to the oscilloscope. use an oscilloscope with at least 400mhz bandwidth. be sure the probe compensation is adjusted properly. im- proper compensation will result in apparent overshoot and/ or ringing if undercompensated, and an apparent slow edge if overcompensated. if the probe ground lead is too long, the output may appear distorted and oscillatory. use probes with short (less than one inch) ground straps or use a coaxial cable connection instead of a probe. do not use x1 or straight probes. their bandwidth is 20mhz or less and capacitive loading is high. the best method is to use 50 w matched terminations as shown in figures 2 and 3. measuring propagation delay figure 2 shows a circuit configuration used for evaluating propagation delay. it uses 50 w matched terminations be- tween the instruments and the cmp100 for best signal integrity. an hp8130a pulse generator is used for the analog input and for the latching signals. the oscilloscope is an hp54503a 500mhz digitizing oscilloscope. this setup was used to generate the dynamic performance waveforms in the typical performance curves section. measuring logic timing figure 3 shows the circuit configuration used for evaluating logic propagation delay. the logic input le1 has been added to the circuit of figure 2. figure 3. circuit for evaluating logic timing. q 1 acom v ref 2 analog in v ref 1 le 1 le 1 q 1 q 2 q 2 le 2 le 2 2 3 v+ 11 12 14 13 4 5 16 16.6 w 16.6 w 16.6 w scope to 50 w generator from 50 w +5v 1? 0.1? 16.6 w 16.6 w 16.6 w 16.6 w to 50 scope w 1 15 9 7 6 ?.2v 0.1? 1? 1? 0.1? 66.5 w 66.5 w ?v cmp100 16.6 w from 50 w generator to 50 w scope 49.9 w 16.6 w 16.6 w 00 w 100 w 1 dcom pwr com v 49.9 w 10 8
10 cmp100 cmp100 applications ate pin receiver a typical ate pin receiver application using cmp100 is illustrated in figure 4. the reference inputs, v ref 1 and v ref 2 are driven by d/a converters (figure 5) while analog input is driven directly from the device under test (dut). window comparator because of its high speed, the cmp100 can be used to make timing measurements on modest-speed digital or high-speed analog waveforms. when the outputs of the cmp100 are combined with a nor gate, a true window comparator function is implemented. refer to gate g3 of figure 6. the output pulse width generated by an input signal passing through the reference levels can be measured. this could be for a rise-time/fall-time measurement (setting the reference levels at 10% and 90% of the signal height) of a modest speed digital waveform, or for the width (and hence the value) of an analog ramp moving between two values from an integrating type signal detector. pulse recovery the window comparator function can also be used to recon- struct pulses that have been degraded. positive and/or nega- tive reference levels can be set up to detect both high and low levels of the pulse. a plot of the response of cmp100 to a narrow pulse with v ref1 = 0v is shown in the typical performance curves section. detecting transients cmp100 can be connected to detect and hold transient occurrences above and below threshold voltages set by v ref 1 and v ref 2 as illustrated in figure 6. the outputs of comparator 1 and comparator 2 are fed back to their le inputs in order to self-latch their outputs. the reset control is used to unlock the outputs after the transient occurrence has been read. the output nor gate g3 combines cmp100 outputs into a single-output window comparator function. figure 5. dual dac7802 (12-bit port), dac7801 (8-bit port) or dac7800 (serial port) d/a converters supply reference inputs to the cmp100. for higher resolution use dac725, dual 16-bit d/a converter. ref102 2 +v cc 4 6 5 1 ina105 3 2 6 +5v +10v to v and/or v refa refb 3 2 1 23 24 18 6 21 4 12 22 dac a db11 db0 data inputs dac7802 +5v v refa v dd dac b dgnd v refb i outb r fbb agnd i outa r fba 10pf 10pf a 2 v ref2 a 1 v ref1 analog in 12 11 14 15 1 3 2 10 8 7 6 le 1 le 1 le 2 le 2 q 1 q 1 q 2 q 2 a 1 , a 2 are 1/2 opa2107. e 0 = e 1 /e 2 , ?.01% c d d/a control circuitry omitted for clarity. cmp100 figure 4. typical ate pin receiver application. driver receiver cmp100 d/a d/a d/a d/a ate computer active load d/a d/a device under test parametric measurement unit
11 cmp100 note that the transient being detected must remain above v ref 1 (or below v ref 2 ) longer than the propagation delay of the cmp100 plus the propagation delay of gates g1 and g2. in an application where only one polarity of transient needs to be captured, comparator 2 (not latched) can be used as the source of the reset control signal to unlock comparator 1 based on a different threshold condition (defined by v ref 2 ) on the analog input signal. this connection will stretch the transient occurrence for the time the v ref 2 condition is present. wide-band amplifiers for analog input signal conditioning in a component test application the analog input of the cmp100 is usually driven directly from the dut output. other applications may require a high-speed buffer or volt- age gain ahead of the cmp100. recommended wide-band- width amplifiers are burr-brown opa603 for up to 10v signals, or opa620/opa621 for very wide-band 3v sig- nals. a high speed instrumentation amplifier such as the burr-brown ina110 can be used for common mode rejec- tion. figure 6. cmp100 used to detect and hold transient occurrences on the output pulse of a device under test, or out-of- limits conditions in a process-variable monitoring application. q 1 acom v ref 2 analog in v ref 1 le 1 le 1 dcom pwr com v q 2 q 2 le 2 le 2 2 3 v+ 11 12 14 13 4 5 16 49.9 w +5v 1? 0.1? 1 15 9 7 6 ?.2v 1? 0.1? 133 w cmp100 v ref 1 v ref 2 q 1 ?.2v g1 g2 g3 reset ??= reset ??= ready mc10102 0.1? 249 w ?v all 49.9 w 10 8

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